This invention relates to cellular processor apparatus in general and more particularly to a processor structure that can support floating point arithmetic operations.
There presently exists many integrated circuits that can implement floating point arithmetic. In view of this there are many manufacturers who supply integrated circuit structures which will perform floating point arithmetic while exhibiting very high performance. The major problem in manufacturing such structures is that the integrated circuit chip cannot be used or employed if there is a manufacturing defect on the chip. In addition, if a defect occurs during the life of the integrated circuit then the circuit also becomes useless.
Essentially, the prior art utilizes a single structure which does not possess spare elements so that when a fault occurs the entire structure becomes worthless. There has been described a number of techniques which are employed in large processing arrays which enable one to fabricate an array structure and then to incorporate on the same integrated circuit chip extra or spare cells. The purpose of the extra cells is to effectively utilize these cells to replace defective cells which may exist on the chip.
Thus the processor structure may be of very low cost because the structure provides very high manufacturing yields through the fault tolerance inherent in it. The architecture consists of a multiplicity of like single bit cells where the number of such cells that cooperate together to form a word is dynamically variable. In this manner the cells can be controlled by suitable instructions to perform arithmetic operations even though the integrated circuit chip contains defective components. Hence according to this procedure, integrated circuits may be fabricated wherein there exists defects at the time of manufacture. These defects will have minimal impact upon system performance. In this manner faulty or defective cells can be made invisible during the operation of the system and, therefore, have very little functional impact on system operation. Such techniques have been described in a co-pending application entitled AN ARRAY RECONFIGURATION APPARATUS AND METHODS PARTICULARLY ADAPTED FOR USE WITH VERY LARGE-SCALE INTEGRATED CIRCUITS filed on Oct. 2, 1985, for S. G. Morton, Ser. No. 782,850. This application essentially describes techniques for forming large integrated circuit arrays as well as processor arrays using spare components and spare wires.
There are many other applications which relate to processor arrays which describe such configurations in great detail. Certain of these applications which are co-pending are also pertinent to the general concepts of processing structures. For example, see the following: ASSOCIATIVE PROCESSOR WITH VARIABLE LENGTH FAST MULTIPLY CAPABILITY, U.S. Pat. No. 4,507,748 issued Mar. 26, 1985, to J. M. Cotton and assigned to the assignee herein. ASSOCIATIVE ARRAY WITH DYNAMICALLY ASSIGNABLE BIT FUNCTIONS, Ser. No. 473,365 filed on Mar. 8, 1983 to S. G. Morton et al and assigned to the assignee herein. ASSOCIATIVE ARRAY WITH FIVE ARITHMETIC PATHS, U.S. Pat. No. 4,580,215 issued Apr. 1, 1986 to S. G. Morton and assigned to the assignee herein.
ARRAY REORGANIZATION WITH INTERNAL CELLULAR CONTROL AND PROCESSING, Ser. No. 797,718 filed on Nov. 13, 1985 by S. G. Morton and assigned to the assignee herein.
ASSOCIATIVE ARRAY WITH TRANSVERSAL HORIZONTAL MULTIPLEXERS, U.S. Pat. No. 4,546,428 issued Oct. 8, 1985, to S. G. Morton and commonly assigned herewith. IMPEDANCE RESTORATION FOR FAST CARRY PROPAGATION, U.S. Pat. No. 4,536,855 issued Aug. 20, 1985, to S. G. Morton.
ADDRESS GENERATION FOR CELLULAR ARRAY PROCESSORS, Ser. No. 803,364 filed on Dec. 2, 1985 by S. G. Morton.
In any event, a processor may consist of a rectangular array of like single bit components or cells, each of which as indicated is implemented in a Very Large Scale Integrated Circuit (VLSI). The cells in the processor array can cooperate to form words of varying size and can communicate in all four directions as right, left, up and down with their neighbors and can also communicate with external devices such as memory for input and output. These devices can perform fixed point and floating point arithmetic. The calculating ability of the processor is a function of the size of the array, the clock rate and other factors as well. In any event, such processing arrays in general are well known. The functions that are typically performed by the commercially available array processor chips include floating multiply, floating add, floating subtract, and floating divide.
In the case of the floating multiplier, the typical implementation in the prior art is to employ a large multiplier array and coupled to the array suitable logic to manipulate the exponent and to extract the mantissa bits from the floating point word. Those bits which are the mantissa bits are then injected back into the multiplier. In this manner, at the output of the multiplier the result is extracted. This result is then packed back into the word with the exponent where the exponent has been modified according to the two input terms.
Similarly, the floating point add unit typically has shift logic that can move the mantissa of a word that is lesser in magnitude so that the result in exponents may be the same. The addition is performed with one very large adder. The exponent is modified and the mantissa and exponent are merged back together for storage. The division operation is generally very time consuming and employs a bit serial at a time and involves relatively little logic other than an adder which would be used in a subtract or add mode.
Based on such prior art devices, it is seen that one requires a large piece of logic. Typically, the multiplier configuration is the largest circuit component, while the shift logic being smaller but also comprising a substantial amount of logic elements. The adder is typically comparable in logic size to the shifter and no defect is permissible in any of this logic. If a defect exits, the chip is completely unusable. Furthermore, the number of bits in the mantissa and the number of bits in the exponent are fixed by the design of the chip. Hence many chips can support the IEEE floating point standard which provides three word lengths of 32 bits, 64 bits and 80 bits. No other word sizes are supported. Generally, it is important to note that the processing speed of these various chips is relatively fast wherein a multiplication for example can be performed in a single operation possibly in the order of a few hundred nanoseconds for a 24-bit by 24-bit multiply as in the case of single precision floating point.
The method and apparatus that will be described in this application is appreciably more time consuming requiring on the order of 100 nanoseconds per step, but it is completely fault tolerant. As will be further explained, another feature of the design is that the floating point structure logic and fixed point logic are implemented into the same structure whereas prior art floating point chips generally only support floating point operation and do not support Boolean operations. The design described will support floating point, fixed point and Boolean operations.